A frequency synthesiser conventionally includes a phase lock loop, in which a dual-modulus prescaler circuit divides the synthesiser output signal frequency by a first factor or a second factor as a function of a selected division mode. Mode selection is performed, for example, by a modulator, such as a sigma delta modulator such that the synthesiser output generates signals at the desired frequency within a determined frequency band.
FIG. 1 shows a conventional dual-modulus prescaler circuit 1. This circuit is capable of dividing the frequency of an input signal CK by a first factor equal to 2 or by a second factor equal to 3 in accordance with the selected mode div.
In order to do this, the prescaler or counter-divider circuit may include two or three standard D-type flip flops 2, 3, 4 and two NOR logic gates 5, 6 in negative feedback arranged between a first flip flop 2 and a second flip flop 3. Each of these flip flops is capable of providing a non-inverted output signal Q and an inverted output signal Qb in accordance with an input signal D. The first and second flip flops 2 and 3 are clocked by the input clock signal CK. A third flip flop 4 clocked by an output signal OUT from second flip flop 3, may also be provided. This third flip flop 4 is only used to ensure proper resynchronisation during a mode change div. The frequency of this output signal OUT of prescaler circuit 1 matches the frequency of input signal CK divided by the first division factor or the second division factor in accordance with the selected mode div.
The first NOR logic gate 5 receives at input the non-inverted output signal Q from the first flip flop 2, and the non-inverted output signal Q from the third flip flop 4 representing the selection of division mode div. The output of this first logic gate 5 is connected to one input of the second NOR logic gate 6, the input of which also receives the non-inverted output signal Q from second flip flop 3. The output of this second logic gate 6 is connected to input D of the second flip flop 3. The output signal OUT from prescaler circuit 1 is supplied to the inverted output Qb of second flip flop 3. This output signal OUT is also the input signal D of first flip flop 2.
If the selected mode div is in state 1, i.e. a high voltage state, prescaler circuit 1 divides the frequency of input signal CK by a first factor equal to 2. Conversely, if the selected mode div is in state 0, i.e. a low voltage state, prescaler circuit 1 divides the frequency of input signal CK by a second factor equal to 3.
Each NOR logic gate 5, 6 is made with two PMOS transistors in series, which are connected in series with two parallel NMOS transistors between a positive supply terminal and a negative supply terminal of a voltage source. One gate of the first PMOS transistor is connected to one gate of the first NMOS transistor to form a first gate input. One gate of the second PMOS transistor is connected to one gate of the second NMOS transistor to form a second gate input. The connection node between the PMOS transistors and NMOS transistors forms the logic gate output.
Due to the use of NOR logic gates with two PMOS transistors in series that are slow, this type of prescaler circuit is not provided to operate normally at a very high frequency, which constitutes a drawback. Moreover, since three standard D-type flip flops are used, this prescaler circuit consumes a significant amount of electrical power.